IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
ELECTRICAL CHARACTERISTICS (continued)
(V IN = (V DD - V SS ) = 48V, R DET = 24.9kω, R CLS = 615ω, and R SL = 60.4kω. RTN, WAD, PG, 2EC , WK , and ULP unconnected, all
voltages are referenced to V SS, unless otherwise noted. T A = T J = -40 N C to +85 N C, unless otherwise noted. Typical values are at
T A = +25 N C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LED Current Programmable
Range
10
20
mA
LED Current with Grounded SL
LED Current Frequency
LED Current Duty Cycle
f ILED
D ILED
V SL = 0V
Normal and ultra-low-power sleep modes
Normal and ultra-low-power sleep modes
20.5
24.5
250
25
28.5
mA
Hz
%
V DD Current Amplitude
Internal Current Duty Cycle
Internal Current Enable Time
Internal Current Disable Time
I VDD
D IVDD
t MPS
t MPDO
Normal sleep mode, V LED = 3.5V
Normal and ultra-low-power sleep modes
Ultra-low-power sleep mode
Ultra-low-power sleep mode
10
80
220
11
75
84
228
12.2
88
236
mA
%
ms
ms
Time V SL must remain below the SL logic
SL Delay Time
t SL
threshold to enter sleep and ultra-low-
5.4
6.0
6.6
s
power modes (MAX5982A)
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
Thermal-Shutdown Hysteresis
T SD
T J rising
T J falling
+150
30
N C
N C
Note
Note
Note
Note
Note
Note
3:
4:
5:
6:
7:
8:
All devices are 100% production tested at T A = +25 N C. Limits over temperature are guaranteed by design.
The input offset current is illustrated in Figure 1.
Effective differential input resistance is defined as the differential resistance between V DD and V SS . See Figure 1.
Classification current is turned off whenever the device is in power mode.
UVLO hysteresis is guaranteed by design, not production tested.
A 20V glitch on input voltage, which takes V DD below V ON shorter than or equal to t OFF_DLY does not cause the
MAX5982A/MAX5982B/MAX5982C to exit power-on mode.
Note 9: Maximum current limit during normal operation is guaranteed by design; not production tested.
Note 10: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an
overload condition across V DD and RTN.
I IN
dR i =
(V INi + 1 - V INi )
(I INi + 1 - I INi )
=
1V
(I INi + 1 - I INi )
I INi + 1
I INi
I OFFSET = I INi -
V INi
dR i
dR i
I OFFSET
V INi
1V
V INi + 1
V IN
Figure 1. Effective Differential Input Resistance/Offset Current
4
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